IPC New Release: IPC-7091 Design and Assembly Process Implementation of 3D Components

The IPC-7091 standard provides useful and practical information to those who are designing, developing or using 3D-packaged semiconductor components or those who are considering 3D package implementation. The 3D semiconductor package may include multiple die elements—some homogeneous and some heterogeneous.

IPC-7091 Design and Assembly Process Implementation of 3D Components

The package may also include several discrete passive SMT devices, some of which are surface mounted and some of which are integrated (embedded) within the components’ substrate structure. Number of pages 108. Released June 2017.

This document describes the design and assembly challenges and ways to address those challenges for implementing 3D component technology. Recognizing the effects of combining multiple uncased semiconductors die elements in a single package format can impact individual component characteristics and can dictate suitable assembly methodology. The information contained in this standard focuses on achieving optimum functionality, process assessment, end-product reliability and repair issues associated with 3D semiconductor package assembly and processing.

Purpose Performance-driven electronic systems continue to challenge companies in search of more innovative semiconductor package methodologies. The key market driver for semiconductor package technology is to provide greater functionality and improved performance without increasing package size. The package interposer is the key enabler. Although glass-reinforced epoxy-based materials and high-density copper interconnect capability will continue to have a primary role for array-configured packaging, there is a trend toward alternative dielectric platforms as well as toward combining multiple functions within the same die element. To address this movement, an increasing number of semiconductor die developed for
advanced applications now require higher I/O with contact pitch variations that are significantly smaller than the mainstream semiconductor products previously in the market. For these applications, companies are developing interposer technologies that can provide interconnect densities far superior to organic-based counterparts.

Target Audience The target audiences for this standard are managers, design/process engineers, and operators who deal with:
• Implementing 3D semiconductor packaging
• Interposer, substrate and PWB design
• Board-level assembly, inspection and repair processes

Intent This standard intends to provide useful and practical information to those who are designing, developing or using 3D-packaged semiconductor components or those who are considering 3D package implementation. The 3D semiconductor package may include multiple die elements—some homogeneous and some heterogeneous. The package may also include several discrete passive SMT devices, some of which are surface mounted and some of which are integrated (embedded) within the components’ substrate structure.

Preview the table of contents .pdf file.

By | 2017-09-28T10:56:37+00:00 28 September 2017|IPC New Release|